1. Technical Field
The present invention relates to a semiconductor package, and more particularly, to a planar multi semiconductor chip package including a memory chip and a processor chip that are connected to each other via through electrodes.
2. Description of the Related Art
A high performance processor such as a CPU or an MPU requires a memory device to/from which a large amount of data can be written/read at high speed, for example, a cache memory device. In a conventional memory device such as a DRAM device, data is read from or written to the DRAM by passing through wires on a system board. In this case, the ratio of the data writing/reading time to the data processing time is increased, thereby decreasing the processing speed of the whole system/processor. In addition, a large system space is required for memory devices and a processor, and thus design rules and the length of wires are increased. The increase in the length of wires causes an increase in input/output power consumption in order to maintain data integrity. In particular, when a CPU is used as a processor, data needs to pass through a controller in order to interface with the memory, and thus the above problems become worse.
One method of solving the above problems is to minimize the length of the wires by stacking a processor chip and a memory chip on the same package substrate.